Regviz

Silicon Labs /EFR32FG23B010F512IM40 /HFXO0_S /CFG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CFG

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32MG24A010F1536GM40/HFXO0_S/CFG#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (XTAL)MODE 0 (ENXIDCBIASANA)ENXIDCBIASANA 0 (DISABLE)SQBUFSCHTRGANA 0 (FORCELFTIMEOUT)FORCELFTIMEOUT

MODE=XTAL, SQBUFSCHTRGANA=DISABLE

Description

No Description

Fields

MODE

Crystal Oscillator Mode

0 (XTAL): crystal oscillator

1 (EXTCLK): external sinusoidal clock can be supplied on XI pin.

2 (EXTCLKPKDET): external sinusoidal clock can be supplied on XI pin (peak detector used).
ENXIDCBIASANA

Enable XI Internal DC Bias
SQBUFSCHTRGANA

Squaring Buffer Schmitt Trigger

0 (DISABLE): Squaring buffer schmitt trigger is disabled

1 (ENABLE): Squaring buffer schmitt trigger is enabled
FORCELFTIMEOUT

Force Low Frequency Timeout

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data